TECHNIQUES AND DEVELOPMENT OF METHODOLOGIES FOR THE REDUCTION OF INTEGRATED ARCHITECTURES OF ASIC DIGITAL COMMUNICATION TRANSCEIVERS

Code:    TIC98-0703
Funder:    Spanish Government
Start date:    1998 October 1st
End date:    2001 September 1st
Keywords:    ASIC, hardware
    
Partners:    E. Bertran Alberti, F. Tarres Ruiz, G. Montoro Lopez, J. Berenguer Sau and R. Ruiz Feliu
SPCOM Participants:    Josep Sala Alvarez
SPCOM Responsible:    Josep Sala Alvarez

Summary

Development of efficient digital signal processing architectures and methodologies for mobile and space communication transceivers. This project funded the access of our research group to hardware design software (SYNOPSYS) and to ASIC fabrication facilities under the EUROPRACTICE European Programme for Academic Institutions.